Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices. The typical structure of an active-matrix liquid crystal display device will be described with reference to FIG. 17. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 17.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 966 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other.
The TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 is on, a grayscale signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes according to a potential difference between each pixel electrode 964 and opposing-substrate electrode 966. This potential difference is held by capacitance 965 of the liquid crystal even after the TFT 963 is turned off, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (grayscale signal voltages) applied to each pixel electrode 964 and a scan line 961 that sends the scan signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitative load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller 940, a required clock CLK, control signals and power-supply voltages, etc., are supplied from the display controller 940, and video data is supplied from the display controller 940 to the data driver 980. At the present time, video is principally digital data.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row (every line) by each scan line, and a grayscale signal voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a binary scan signal, it is required that the data driver 980 drives the data line 962 with grayscale signal voltages of multiple levels that conform to the number of gray levels. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a grayscale signal voltage and an operational amplifier for amplifying the grayscale signal voltage and outputting the amplified signal to the data line 962.
With the progress that has been made in raising image quality (increasing the number of colors) in liquid crystal display devices, there is now growing demand for at least 260,000 colors (video data of six bits per each of the colors R, G, B) and preferably 26,800,000 colors (video data of eight bits per each of the colors R, G, B) or more.
For this reason, a data driver that outputs a grayscale signal voltage corresponding to multiple-bit video data is such that the circuitry of the DAC is of larger scale. This increases the chip area of the data-driver LSI chip and invites an increase in cost. This problem will be elaborated below.
FIG. 18 is a diagram illustrating an example of the general structure of the data driver 980 shown in FIG. 17. Here the main portions of the data driver 980 are depicted as blocks. As shown in FIG. 18, the data driver 980 includes a latch address selector 981, a latch 982, a grayscale voltage generating circuit 983, decoders 984 and buffer circuits 985.
The latch address selector 981 decides data latch timing based upon a clock signal CLK. The latch 982 latches video digital data based upon the data latch timing and outputs data to each of the decoders 984 at all at once in response to an STB (strobe) signal. The grayscale voltage generating circuit 983 generates grayscale voltages the number of levels whereof corresponds to the video data. The decoders 984 each select and output one grayscale voltage that corresponds to the data input thereto, and the buffer circuits 985, to which the grayscale voltages output from the decoders 984 are applied, respectively, subject these voltages to current amplification and output the results as output voltage Vout.
By way of example, if 6-bit video data is input, the number of levels is 64 and the grayscale voltage generating circuit 983 generates grayscale voltages having 64 levels. The decoders 984 select one grayscale voltage from these grayscale voltages of 64 levels.
If 8-bit video data is input, on the other hand, then the number of levels is 256, the grayscale voltage generating circuit 983 generates grayscale voltages having 256 levels and the decoders 984 select one grayscale voltage from these grayscale voltages of 256 levels.
Thus, an increase in the number of bits of video data is accompanied by an increase in the scale of the circuitry of the grayscale voltage generating circuit 983 and decoders 984. For example, if the number of bits is increased from six to eight, the scale of the circuitry increases by four times or more. Accordingly, an increase in the number of bits of video data increases the chip area of the data driver LSI chip and raises cost.
An arrangement adapted to suppress an increase in the chip area of a data driver LSI chip even if the number of bits is increased has been proposed in Patent Document 1, described later. FIG. 19 illustrates an example of the arrangement proposed in Patent Document 1 (FIG. 19 corresponds to FIG. 4 in Patent Document 1).
As shown in FIG. 19, this data driver differs from that of FIG. 18 in terms of a grayscale voltage generating circuit 986, decoders 987 and buffer circuits 988. The grayscale voltage generating circuit 986 shown in FIG. 19 generates grayscale voltages at intervals of two levels, thereby making the number of grayscale voltage lines of the decoders 987 approximately half the number of decoders 984 in FIG. 18. The decoders 987 each select two grayscale voltages in accordance with the video data and output these grayscale voltages to the buffer circuits 988. Each buffer circuit 988 is capable of amplifying and outputting the two input grayscale voltages and grayscale voltages intermediate these two grayscale voltages.
By providing the buffer circuits 988 each of which receives two grayscale voltages and outputs one of these two grayscale voltages and a voltage intermediate these voltages, the arrangement described in Patent Document 1 seeks to halve the number of grayscale voltage lines of the decoders 987, reduce the scale of the circuitry of the decoders 987 and reduce area, i.e., lower cost. Accordingly, an increase in the chip area of the data driver LSI chip owing to an increase in the number of bits in the video data signal can be suppressed to some degree.
It should be noted that an arrangement of the kind shown in FIG. 5(B) of Patent Document 1 has been proposed as a differential amplifier that is ideal for the buffer circuit 988. In the arrangement shown in FIG. 5(B) of Patent Document 1, the output of a differential pair is the input end of a diode-connected current mirror. Although it may be thought that this is an arrangement that does not function as a differential amplifier, it can be inferred that the features of the differential amplifier proposed in Patent Document 1 are those of the differential amplifier illustrated in FIG. 20 (this is based upon the considerations of the inventor). Further, FIG. 20 is equivalent to a differential amplifier implemented using two differential pairs in FIG. 5 of Patent Document 2, described later.
As shown in FIG. 20, transistors 901 and 902 constituting a first differential pair and transistors 903 and 904 constituting a second differential pair are connected in parallel. Each differential pair is driven by a common current source 907. Grayscale voltages V(T1) and V(T2) are input to the gates of the transistors 901 and 903, respectively, the gates of the transistors 902 and 904 are coupled together and the voltage output Vout of the differential amplifier is fed back to the input. The output pair of the first and second differential pairs is connected to respective ones of the input and output ends of a current mirror (911, 912) so that an amplifying operation conforming to the output signal common to the first and second differential pairs is performed.
The differential amplifier having such a configuration is such that the following holds:
the output voltage Vout is equal to the input voltages V(T1) and V(T2) when the voltages V(T1) and V(T2) are identical; and
the output voltage Vout is a voltage intermediate the voltages V(T1) and V(T2) when the voltages V(T1) and V(T2) are different.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-34234A (FIG. 4)
[Patent Document 2]
U.S. Pat. No. 5,396,245 (FIG. 5)
A first problem pointed out (see the description in section [0113] on page 13 of Patent Document 1) with regard to the differential amplifier shown in FIG. 20 is that in a case where the amplifier outputs a voltage intermediate the two input voltages V(T1) and V(T2), the voltage shifts and takes on a value offset toward either of the two input voltages if the voltage difference between the two input values becomes large.
Further, in a case where the data driver of FIG. 19 uses the differential amplifier shown in FIG. 20, the reduction in number of grayscale voltage lines of the decoders 987 that can be achieved is limited to half that of the decoders 984 in FIG. 18. A greater reduction in number of grayscale voltages cannot be attained and a reduction in area cannot be implemented.